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MB90335 Series
* Instruction system * Data types: Bit, Byte, Word, Long word * Addressing mode (23 types) * Enhanced high-precision computing with 32-bit accumulator * Enhanced Multiply/Divide instructions with sign and the RETI instruction * Instruction system compatible with high-level language (C language) and multi-task * Employing system stack pointer * Instruction set symmetry and barrel shift instructions * Program Patch Function (2 address pointer) * 4-byte instruction queue * Interrupt function * Priority levels are programmable * 20 interrupts function * Data transfer function * Extended intelligent I/O service function (EI2OS) : Maximum of 16 channels * DMAC : Maximum 16 channels * Low Power Consumption Mode * Sleep mode (with the CPU operating clock stopped) * Time-base timer mode (with the oscillator clock and time-base timer operating) * Stop mode (with the oscillator clock stopped) * CPU intermittent operation mode (with the CPU operating at fixed intervals of set cycles) * Package * LQFP-64P (FPT-64P-M23 : 0.65 mm pin pitch) * Process : CMOS technology * Operation guaranteed temperature: - 40 C to + 85 C (0 C to + 70 C when USB is in use) (Continued)
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PRODUCT LINEUP
Part number Type ROM capacity RAM capacity Emulator-specific power supply * MB90V330A For evaluation No 28 Kbytes Used bit Number of basic instructions Minimum instruction execution time Addressing type Program Patch Function Maximum memory space MB90F337 Built-in Flash Memory MB90337 Built-in MASK ROM
64 Kbytes 4 Kbytes : 351 instructions : 41.7 ns / at oscillation of 6 MHz (When 4 times are used : Machine clock of 24 MHz) : 23 types : For 2 address pointers : 16 Mbytes
CPU functions
Ports
I/O Ports(CMOS) Max 45 ports Equipped with full-duplex double buffer Clock synchronous or asynchronous operation selectable. It can also be used for I/O serial. Built-in special baud-rate generator Built-in 2 channels 16-bit reload timer operation Built-in 1 channel 8/16-bit PPG timer (8-bit mode x 4 channels, 16-bit mode x 2 channels) 16-bit PWC timer x 1 channel 8 channels Interrupt factor : "L""H" edge /"H""L" edge /"L" level /"H" level selectable 1 channel 1 channel USB function (correspond to USB 2.0 Full Speed) USB HOST function 8 ports (Excluding UTEST and I/O for I2C) Sleep mode/Timebase timer mode/Stop mode/CPU intermittent mode CMOS 3.3 V 0.3 V (at maximum machine clock 24 MHz)
UART
16-bit reload timer Multi-functional timer DTP/External interrupt I2C
Extended I/O serial interface 1 channel USB Withstand voltage of 5 V Low Power Consumption Mode Process Operating voltage VCC
* : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used. Please refer to the MB2147-01 or MB2147-20 hardware manual (3.3 Emulator-dedicated Power Supply Switching) about details.
PACKAGES AND PRODUCT MODELS
Package FPT-64P-M23 (LQFP) PGA-299C-A01 (PGA) : Yes : No MB90337 MB90F337 MB90V330A
Note : See " PACKAGE DIMENSIONS" for details. 4 DS07-13735-4E
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PIN ASSIGNMENT
(TOP VIEW)
P51 P41/TOT0 P40/TIN0 P67/INT7/SDA0 P66/INT6/SCL0 P65/INT5/PWC P64/INT4/SCK P63/INT3/SOT P62/INT2/SIN P61/INT1 P60/INT0 P27/PPG3 P26/PPG2 P25/PPG1 P50 Vcc UTEST Vss DVM DVP Vcc Vss HVM HVP Vcc HCON P42/SIN0 P43/SOT0 P44/SCK0 P45/SIN1 P46/SOT1 P47/SCK1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
Vss X1 X0 P24/PPG0 P23 P22 P21 P20 P17 P16 P15 P14 P13 P12 P11 P10
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P52 P53 Vss MD2 MD1 MD0 RST P54 P00 P01 P02 P03 P04 P05 P06 P07
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
(FPT-64P-M23)
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MB90335 Series
(Continued) Type H
P-ch Pout
Circuit Open drain control signal
Remarks * CMOS output * CMOS hysteresis input (With input interception function at standby) With open drain control signal
N-ch
Nout
CMOS hysteresis input Standby control signal I
Control signal R P-ch Pout
* CMOS output * CMOS input (With input interception function at standby) * Programmable input pull-up resistor
N-ch
Nout
CMOS input Standby control signal J D + input
D+ D-
USB I/O pin
D - input Differential input Full D + output Full D - output Low D + output Low D - output Direction Speed
K
P-ch Pout
N-ch
Nout
* CMOS output * CMOS input (With input interception function at standby)
CMOS input Standby control signal
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HANDLING DEVICES
1. Preventing latch-up and turning on power supply
latch-up may occur on CMOS IC under the following conditions: * If a voltage higher than VCC or lower than VSS is applied to input and output pins. * A voltage higher than the rated voltage is applied between VCC and VSS. When latch-up occurs, power supply current increases rapidly and might thermally damage elements. When using CMOS IC, take great care to prevent the occurrence of latch-up.
2. Treatment of unused pins
Leaving unused input pins unconnected can cause abnormal operation or latch-up, leading to permanent damage. Unused input pins should always be pulled up or down through resistance of at least 2 k. Any unused input/output pins may be set to output mode and left open, or set to input mode and treated the same as unused input pins. If there is unused output pin, make it to open.
3. About the attention when the external clock is used
Even when using an external clock signal, an oscillation stabilization delay is applied after a power-on reset or when recovering from sub-clock or stop mode. When suing an external clock, 25 MHz should be the upper frequency limit. The following figure shows a sample use of external clock signals. * Using external clock
X0
OPEN
X1
4. Treatment of power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. However, you must connect the pins to external power supply and a ground line to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. Moreover, connect the current supply source with the VCC and VSS pins of this device at the low impedance. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1 F between VCC and VSS pins near this device.
5. About crystal oscillator circuit
Noise near the X0 and X1 pins may cause the device to malfunction. Design the printed circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator) , and the bypass capacitor to ground are located as close to the device as possible. It is strongly recommended to design the PC board artwork with the X0 and X1 pins surrounded by ground plane because stable operation can be expected with such a layout. Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
6. Caution on Operations during PLL Clock Mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs. 10 DS07-13735-4E
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BLOCK DIAGRAM
X0, X1 RST MD0 to MD2
Clock control circuit Interrupt controller
RAM ROM
F2MC-16LX CPU
8/16-bit PPG timer ch.0 to ch.3* 16-bit PWC
PPG0 to PPG3
SIN0, SIN1 SOT0, SOT1 SCK0, SCK1 SCL0 SDA0
PWC SIN SOT SCK
UART/SIO ch.0, ch.1 I2C
Internal data bus
SIO
DMAC
TOT0 TIN0 DVP DVM HVP HVM HCON UTEST INT0 to INT7
16-bit reload timer
USB (function) (HOST)
External interrupt
I/O port (port 0, 1, 2, 4, 5, 6)
P00 P07
P10 P17
P20 P27
P40 P47
P50 P54
P60 P67
* : Channel for use in 8-bit mode. 2 channels (ch.1, ch.3) are used in 16-bit mode. Note : I/O ports share pins with peripheral function (resources) . For details, refer to " PIN ASSIGNMENT" and " PIN DESCRIPTION". Note also that pins used for peripheral function (resources) cannot serve as I/O ports.
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MEMORY MAP
Single chip mode (with ROM mirror function)
MB90V330A
FFFFFFH FF0000H
MB90F337
FFFFFFH FF0000H
MB90337
FFFFFFH FF0000H
ROM (FF bank)
ROM (FF bank)
ROM (FF bank)
00FFFFH 008000H 007FFFH 007900H 007100H
ROM area (image of FF bank)
00FFFFH 008000H 007FFFH 007900H
ROM area (image of FF bank)
00FFFFH 008000H 007FFFH 007900H
ROM area (image of FF bank)
Peripheral area
Peripheral area
Peripheral area
RAM area (28 Kbytes)
000100H 0000FBH
001100H
Register
000100H 0000FBH
RAM area (4 Kbytes) Register
001100H
000100H 0000FBH
RAM area (4 Kbytes) Register
Peripheral area
000000H 000000H
Peripheral area
000000H
Peripheral area
Notes : * When the ROM mirror function register has been set, the mirror image data at higher addresses ("FF8000H to FFFFFFH" ) of bank FF is visible from the higher addresses ("008000H to 00FFFFH") of bank 00. * The ROM mirror function is effective for using the C compiler small model. * The lower 16-bit addresses of bank FF are equivalent to those of bank 00. Since the ROM area in bank FF exceeds 48 Kbytes, however, the mirror image of all the data in the ROM area cannot be reproduced in bank 00. * When the C compiler small model is used, the data table mirror image can be shown at "008000H to 00FFFFH" by storing the data table at "FF8000H to FFFFFFH". Therefore, data tables in the ROM area can be referred without declaring the far addressing with the pointer.
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F2MC-16L CPU PROGRAMMING MODEL
* Dedicated register
AH AL USP SSP PS PC DPR PCB DTB USB SSB ADB 8-bit 16-bit 32-bit
Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User stack bank register System stack bank register Additional data bank register
* General purpose registers
MSB 000180H + RP x 10H RW0 RL0 RW1 RW2 RL1 RW3 R1 R3 R5 R7 R0 R2 R4 R6 RW4 RL2 RW5 RW6 RL3 RW7 16-bit LSB
* Processor status
Bit 15 PS ILM 13 12 RP 87 CCR 0
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Address 000066H to 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H to 00009AH 00009BH 00009CH 00009DH 00009EH 00009FH 0000A0H 0000A1H 0000A2H 0000A3H 0000A4H 0000A5H to 0000A7H 0000A8H 0000A9H 0000AAH 0000ABH 0000ACH 0000ADH 0000AEH 0000AFH DERL DERH FMCS DMA Enable Register Lower DMA Enable Register Upper Flash Memory Control Status Register Prohibited (Continued) WDTC TBTC DSSR DMA Stop Status Register Prohibited Watchdog Timer Control Register Time-base Timer Control Register Prohibited R/W R/W R/W DMAC 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R/W R/W Watchdog Timer X - XXX 1 1 1B Time-base Timer 1 - - 0 0 1 0 0B DCSR DSRL DSRH PACSR DIRR LPMCR CKSCR ROMM IBSR0 IBCR0 ICCR0 IADR0 IDAR0 Register abbreviation Register Prohibited ROM Mirroring Function Selection Register I2C Bus Status Register I C Bus Control Register I C Bus Clock Control Register I C Bus Address Register I C Bus Data Register Prohibited DMA Descriptor Channel Specification Register DMA Status Register Lower DMA Status Register Upper Program Address Detection Control Status Register Delayed Interrupt Source generate/ release Register Low Power Consumption Mode Control Register Clock Selection Register Prohibited R/W DMAC 0 0 0 0 0 0 0 0B R/W R/W R/W R/W R/W R/W R/W Address Match Detection Delayed Interrupt Low Power Consumption control circuit Clock DMAC 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - - - - - 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
2 2 2 2
Read/ Resource name Write
Initial Value
W R R/W R/W R/W R/W
ROM Mirror Function Selection Module
- - - - - - 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
I C Bus Interface XX 0 XXXXXB XXXXXXXXB XXXXXXXXB
2
Flash Memory I/F 0 0 0 X 0 0 0 0B
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Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H 0000C1H 0000C2H 0000C3H 0000C4H 0000C5H 0000C6H 0000C7H 0000C8H 0000C9H 0000CAH 0000CBH 0000CCH 0000CDH 0000CEH 0000CFH 0000D0H 0000D1H
Register abbreviation ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 HCNT0 HCNT1 HIRQ HERR HSTATE HFCOMP
Register Interrupt Control Register 00 Interrupt Control Register 01 Interrupt Control Register 02 Interrupt Control Register 03 Interrupt Control Register 04 Interrupt Control Register 05 Interrupt Control Register 06 Interrupt Control Register 07 Interrupt Control Register 08 Interrupt Control Register 09 Interrupt Control Register 10 Interrupt Control Register 11 Interrupt Control Register 12 Interrupt Control Register 13 Interrupt Control Register 14 Interrupt Control Register 15 Host Control Register 0 Host Control Register 1 Host Interruption Register Host Error Status Register Host State Status Register SOF Interrupt FRAME Compare Register Retry Timer Setting Register Host Address Register EOF Setting Register FRAME Setting Register Host Token End Point Register Prohibited
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Interrupt Controller
0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 1 1B XX 0 1 0 0 1 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
HRTIMER HADR HEOF HFRAME HTOKEN
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
USB HOST
0 0 0 0 0 0 0 0B XXXXXX 0 0B X 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XX 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX 0 0 0B 0 0 0 0 0 0 0 0B 1 0 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B (Continued)
UDCC
UDC Control Register
USB Function
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Address 0000D2H 0000D3H 0000D4H 0000D5H 0000D6H 0000D7H 0000D8H 0000D9H 0000DAH 0000DBH 0000DCH 0000DDH 0000DEH 0000DFH 0000E0H 0000E1H 0000E2H 0000E3H 0000E4H 0000E5H 0000E6H 0000E7H 0000E8H 0000E9H 0000EAH 0000EBH 0000ECH 0000EDH 0000EEH 0000EFH 0000F0H 0000F1H 0000F2H 0000F3H 0000F4H 0000F5H 0000F6H 0000F7H 0000F8H 0000F9H
Register abbreviation EP0C EP1C EP2C EP3C EP4C EP5C TMSP UDCS UDCIE EP0IS EP0OS EP1S EP2S EP3S EP4S EP5S EP0DT EP1DT EP2DT EP3DT EP4DT
Register EP0 Control Register EP1 Control Register EP2 Control Register EP3 Control Register EP4 Control Register EP5 Control Register Time Stamp Register UDC Status Register UDC Interrupt Enable Register EP0I Status Register EP0O Status Register EP1 Status Register EP2 Status Register EP3 Status Register EP4 Status Register EP5 Status Register EP0 Data Register EP1 Data Register EP2 Data Register EP3 Data Register EP4 Data Register
Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W, R R/W R R/W R R/W R R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial Value 0 1 0 0 0 0 0 0B XXXX 0 0 0 0B 0 0 0 0 0 0 0 0B 0 1 1 0 0 0 0 1B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 1 0 0 0 0 0 0B 0 1 1 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXX0 0 0B XX0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 1 0 XXX 1 XXB 0 XXXXXXXB 1 0 0 XX 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 XB XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB 1 0 0 0 0 0 0 0B XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB (Continued)
USB Function
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MB90335 Series
Address 0000FAH 0000FBH 0000FCH to 0000FFH 000100H to 001100H 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 007900H 007901H 007902H 007903H 007904H 007905H 007906H 007907H 007908H to 00790BH 00790CH 00790DH 00790EH 00790FH to 00791FH
Register abbreviation EP5DT
Register EP5 Data Register
Read/ Write R/W R/W Prohibited
Resource name USB Function
Initial Value XXXXXXXXB XXXXXXXXB
RAM Area Program Address Detection Register ch.0 Lower PADR0 Program Address Detection Register ch.0 Middle Program Address Detection Register ch.0 Upper Program Address Detection Register ch.1 Lower PADR1 Program Address Detection Register ch.1 Middle Program Address Detection Register ch.1 Upper PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PPG Reload Register Lower ch.0 PPG Reload Register Upper ch.0 PPG Reload Register Lower ch.1 PPG Reload Register Upper ch.1 PPG Reload Register Lower ch.2 PPG Reload Register Upper ch.2 PPG Reload Register Lower ch.3 PPG Reload Register Upper ch.3 Prohibited FWR0 FWR1 SSR0 Flash Memory Program Control Register 0 Flash Memory Program Control Register 1 Sector Conversion Setting Register Prohibited (Continued) R/W R/W R/W Flash Flash Flash 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 XXXXX0B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W PPG ch.0 PPG ch.1 PPG ch.2 PPG ch.3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address Match Detection
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(Continued) Address 007920H 007921H 007922H 007923H 007924H 007925H 007926H 007927H 007928H to 007FFFH * Explanation on read/write R/W : Readable and Writable R : Read only W : Write only * Explanation of initial values 0 : Initial value is "0". 1 : Initial value is "1". X : Initial value is undefined. : Initial value is undefined (None). Note : No I/O instruction can be used for registers located between 007900H and 007FFFH. Register abbreviation DBAPL DBAPM DBAPH DMACS DIOAL DIOAH DDCTL DDCTH Register DMA Buffer Address Pointer Lower 8-bit DMA Buffer Address Pointer Middle 8-bit DMA Buffer Address Pointer Upper 8-bit DMA Control Register DMA I/O Register Address Pointer Lower 8-bit DMA I/O Register Address Pointer Upper 8-bit DMA Data Counter Lower 8-bit DMA Data Counter Upper 8-bit Prohibited Read/ Write R/W R/W R/W R/W R/W R/W R/W R/W DMAC Resource name Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
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INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
Interrupt source Reset INT 9 instruction Exceptional treatment USB Function1 USB Function2 USB Function3 USB Function4 USB HOST1 USB HOST2 I2C ch.0 DTP/External interrupt ch.0/ch.1 No DTP/External interrupt ch.2/ch.3 No DTP/External interrupt ch.4/ch.5 PWC/Reload timer ch.0 DTP/External interrupt ch.6/ch.7 No No No No No PPG ch.0/ch.1 No PPG ch.2/ch.3 No No No No UART (Send completed) ch.0/ch.1 Extended serial I/O UART(Reception completed) ch.0/ch.1 Time-base timer Flash memory status Delay interrupt output module x x x x x x EI2OS DMAC support x x x x x x x x x x x x x 0, 1 2 to 6*2 x x x x x x x x 14 x x x 13 9 12 x x x Interrupt vector Number* #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42
1
Interrupt control register ICR Address
Priority High
Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H
08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH
ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH
ICR14 0000BEH
ICR15 0000BFH
Low
(Continued) 22 DS07-13735-4E
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(Continued) : Available. EI2OS stop function provided (The interrupt request flag is cleared by the interrupt clear signal. With a stop request). : Available (The interrupt request flag is cleared by the interrupt clear signal). : Available when any interrupt source sharing ICR is not used. x : Unavailable *1 : If the same level interrupt is output simultaneously, the lower interrupt factor of interrupt vector number has priority. *2 : Ch.2 and ch.3 can be used in USB HOST operation. Notes : * If the same interrupt control register (ICR) has two interrupt factors and the use of the EI2OS is permitted, the EI2OS is activated when either of the factors is detected. As any interrupt other than the activation factor is masked while the EI2OS is running, it is recommended that you should mask either of the interrupt requests when using the EI2OS. * The interrupt flag is cleared by the EI2OS interrupt clear signal for the resource that has two interrupt factors in the same interrupt control register (ICR). * If a resource has two interrupt sources for the same interrupt number, both of the interrupt request flags are cleared by the DMAC interrupt clear signal. Therefore, when you use either of two interrupt factors for the DMAC function, another interrupt function is disabled. Set the interrupt request permission bit to " 0 " in the appropriate resource, and take measures by software polling.
CONTENT OF USB INTERRUPTION FACTOR
USB interrupt factor USB function 1 USB function 2 USB function 3 USB function 4 USB HOST1 USB HOST2 End Point 1-5 * SUSP, SOF, BRST, WKOP, COHF SPIT DIRQ, CHHIRQ, URIRQ, RWKIRQ SOFIRQ, CMPIRQ Details End Point 0-IN, End Point 0-OUT
* : End Point 1and 2 can be used in USB HOST operation.
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MB90335 Series
USB
1. USB Function
The USB function is an interface supporting the USB (Universal Serial Bus) communications protocol. Features of USB function * Supports USB 2.0 Full Speed * Supports full speed (12 Mbps). * The device status is auto-answer. * Bit stripping, bit stuffing, and automatic generation and check of CRC5 and CRC16. * Toggle check by data synchronization bit. * Automatic response to all standard commands except Get/SetDescriptor and SynchFrame commands (these three commands can be processed the same way as the class vendor commands). * The class vendor commands can be received as data and responded via firmware. * Supports up to a maximum of six EndPoints (EndPoint0 is fixed to control transfer). * Two built-in transfer data buffers for each end point (one IN buffer and one OUT buffer for end point 0). * Supports automatic transfer mode for transfer data via DMA (except buffers for EndPoint0).
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2. USB HOST
USB HOST provides minimal host operations required and is a function that enables data to be transferred between devices without PC intervention. * Features of USB HOST * Automatic detection of Low Speed/Full Speed transfer * Low Speed/Full Speed transfer support * Automatic detection of connection and cutting device * Reset sending function support to USB-bus * Support of IN/OUT/SETUP/SOF token * In-token handshake packet automatic transmission (excluding STALL) * Handshake packet automatic detection at out-token * Supports a maximum packet length of 256 bytes * Error (CRC error/toggle error/time-out) various supports * Wake-Up function support * Restrictions on USB HOST USB HOST HUB support Bulk transfer Transfer Control transfer Interrupt transfer Isochronous transfer Transfer speed PRE packet support SOF packet support CRC error Error Toggle error Time-out Maximum packet < receive data Detection of connection and cutting of device Transfer speed detection x : Supported : Not supported Low Speed Full Speed x x *
* : Only supports full speed, and supports hubs up to one level.
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MB90335 Series
SECTOR CONFIGURATION OF FLASH MEMORY
512 Kbits flash memory is located in FFH bank in the CPU memory map. Flash Memory CPU address Writer address *
FF0000H FF0FFFH FF1000H FF1FFFH FF2000H SA2 (4 Kbytes) SA3 (4 Kbytes) SA4 (16 Kbytes) SA5 (16 Kbytes) FF2FFFH FF3000H FF3FFFH FF4000H FF7FFFH FF8000H FFBFFFH FFC000H SA6 (4 Kbytes) SA7 (4 Kbytes) SA8 (4 Kbytes) FFCFFFH FFD000H FFDFFFH FFE000H FFEFFFH FFF000H SA9 (4Kbytes) FFFFFFH 70000H 70FFFH 71FFFH 72000H 72FFFH 73000H 73FFFH 74000H 77FFFH 78000H 7BFFFH 7CFFFH 7D000H 7DFFFH 7E000H 7EFFFH 7F000H 7FFFFH Upper Bank 7C000H Lower Bank 71000H
SA0 (4 Kbytes) SA1 (4 Kbytes)
* : Flash memory writer address indicates the address equivalent to the CPU address when data is written to the flash memory using a parallel writer. Programming and erasing by the general-purpose parallel programmer are executed based on writer addresses.
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ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage*1 Symbol VCC Rating Min VSS - 0.3 VSS - 0.3 Input voltage*1 VI VSS - 0.3 - 0.5 Output voltage*1 Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature VO ICLAMP ICLAMP IOL1 IOL2 IOLAV1 IOLAV2 IOL IOLAV IOH1 IOH2 IOHAV1 IOHAV2 IOH IOHAV Pd TA Tstg VSS - 0.3 - 0.5 - 2.0 - 40 - 55 - 55 Max VSS + 4.0 VSS + 4.0 VSS + 6.0 VSS + 4.5 VSS + 4.0 VSS + 4.5 +2.0 20 10 43 4 15/4.5 100 50 - 10 - 43 -4 -15/-4.5 - 100 - 50 270 + 85 + 150 + 125 Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mW C C C USB I/O *7 *7 Other than USB I/O*5 USB I/O*5 *6 USB-IO (Full speed/Low speed) *6 *2 N-ch open-drain (Withstand voltage I/O of 5 V)*3 USB I/O *2 USB I/O *4 *4 Other than USB I/O*5 USB I/O*5 *6 USB-IO (Full speed/Low speed) *6 Remarks
*1 : The parameter is based on VSS = 0.0 V. *2 : VI and VO must not exceed VCC + 0.3 V. However, if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *3 : Applicable to pins : P60 to P67, UTEST (Continued) DS07-13735-4E 27
MB90335 Series
(Continued) *4 : * * * * * * * * * * Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P40 to P47, P50 to P54 Use within recommended operating conditions. Use at DC voltage (current) The +B signal should always be applied a limiting resistance placed between the +B signal and the microcontroller. The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. Care must be taken not to leave the +B input pin open. Note that analog system input/output pins other than P60 to P67, DVP, DVM, HVP, HVM, UTEST, HCON
* Sample recommended circuits: * Input/output equivalent circuits Protective diode
VCC
Limiting resistance
P-ch
+B input (0 V to 16 V)
N-ch
R
*5 : A peak value of an applicable one pin is specified as a maximum output current. *6 : The average output current specifies the mean value of the current flowing in the relevant single pin during a period of 100 ms. *7 : The average total output current specifies the mean value of the currents flowing in all of the relevant pins during a period of 100 ms. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
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2. Recommended Operating Conditions
(VSS = 0.0 V) Parameter Symbol Value Min 3.0 Power supply voltage VCC VIH VIHS1 Input "H" voltage VIHS2 VIHM VIHUSB VIL Input "L" voltage VILS VILM VILUSB Differential input sensitivity Differential common mode input voltage range Operating temperature VDI 2.7 1.8 0.7 VCC 0.8 VCC 0.8 VCC VCC - 0.3 2.0 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS 0.2 Max 3.6 3.6 3.6 VCC + 0.3 VCC + 0.3 VSS + 5.3 VCC + 0.3 VCC + 0.3 0.3 VCC 0.2 VCC VSS + 0.3 0.8 2.5 + 85 + 70 Unit V V V V V V V V V V V V V Remarks At normal operation (When using USB) At normal operation (When not using USB) Hold state of stop operation CMOS input pin CMOS hysteresis input pin N-ch open-drain (Withstand voltage I/O of 5 V)* MD pin input USB pin input CMOS input pin CMOS hysteresis input pin MD pin input USB pin input USB pin input
VCM
0.8 - 40 0
V C C
USB pin input When not using USB When using USB
TA
* : Applicable to pins : P60 to P67, UTEST WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand.
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3. DC Characteristics
(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Output pins other than P60 to P67, HVP, HVM, DVP, DVM HVP, HVM, DVP, DVM Output "L" voltage Conditions Value Min
VCC - 0.5
Typ
Max Vcc
Unit Remarks
Output "H" voltage
IOH = -4.0 mA
V
VOH
RL = 15 k 5%
2.8 Vss 0 - 10 -5 25
50 0.1
3.6
Vss + 0.4
V V V A A k A
VOL
Output pins other than HVP, HVM, DVP, IOL = 4.0 mA DVM HVP, HVM, DVP, DVM RL = 1.5 k 5%
0.3 + 10 +5 100 10
Input leak current Pull-up resistance Open drain output leak current
IIL
Input pins other than VCC = 3.3 V, P60 to P67, HVP, Vss < VI < VCC HVM, DVP, DVM HVP, HVM, DVP, DVM VCC = 3.3 V, TA = + 25 C VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At USB operating (USTP = 0) VCC = 3.3 V, Internal frequency 24 MHz, At normal operating At non-operating USB (USTP = 1) VCC VCC = 3.3 V, Internal frequency 24 MHz, At sleep mode VCC = 3.3 V, Internal frequency 24 MHz, At timer mode VCC = 3.3 V, Internal frequency 3 MHz, At timer mode TA = +25 C, At stop mode
RPULL
P00 to P07, P10 to P17
ILIOD P60 to P67
55 50 50 45
65 60 60 55
mA MB90F337 mA MB90337 mA MB90F337 mA MB90337
ICC
Power supply current
ICCS
25
40
mA
3.5
10
mA
ICTS

1.0 1
2.0 40
mA A (Continued)
ICCH
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(Continued) Parameter Input capacitance Pull-up resistor Pull-down resistor USB I/O output impedance Symbol CIN Rup Pin name Other than Vcc and Vss RST (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Value Conditions Unit Remarks Min Typ Max VCC = 3.0 V At TA = +25 C 25 25 3 5 50 50 15 100 100 14 pF k k MB90337
Rdown MD2 ZUSB DVP, DVM HVP, HVM
Note : P60 to P67 are N-ch open-drain pins usually used as CMOS.
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4. AC Characteristics
(1) Clock input timing (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Clock frequency Clock cycle time Input clock pulse width Input clock rise time and fall time Internal operating clock frequency Internal operating clock cycle time Symbol fCH tHCYL PWH PWL tcr tcf fCP tCP Pin name X0, X1 X0, X1 X0 X0 Value Min 6 166.7 10 3 42 Typ 6 166.7 Max 24 41.7 5 24 333 Unit Remarks
MHz When oscillator is used MHz External clock input ns ns ns ns When oscillator is used External clock input A reference duty ratio is 30% to 70%. At external clock
MHz When main clock is used ns When main clock is used
* Clock Timing
tHCYL 0.8 VCC
X0
0.2 VCC PWH tcf PWL tcr
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* PLL operation guarantee range Relation between power supply voltage and internal operation clock frequency PLL operation guarantee range Power supply voltage VCC (V)
3.6
3.0 2.7
Normal operation assurance range
3 6 12 24
Internal clock fCP (MHz) Note : When the USB is used, operation is guaranteed at voltages between 3.0 V to 3.6 V. Relation between internal operation clock frequency and external clock frequency
24
4x
Internal clock fCP (MHz)
2x
12
External clock
6
1x
3
6
24
External clock FC (MHz) The AC standards provide that the following measurement reference voltages. * Output signal waveform * Input signal waveform Hysteresis input pin
0.8 VCC 0.2 VCC
Output pin
2.4 V 0.8 V
Hysteresis input/other than MD input pin
0.7 VCC 0.3 VCC
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MB90335 Series
(2) Reset (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Symbol Pin name Conditions Value Min Max Unit Remarks At normal operating, At time base timer mode, At main sleep mode, At PLL sleep mode At stop mode
Reset input time
500 tRSTL RST Oscillation time of oscillator* + 500 ns
ns
s
* : Oscillation time of oscillator is the time that the amplitude reaches 90 %. It takes several milliseconds to several dozens of milliseconds on a crystal oscillator, several hundreds of microseconds to several milliseconds on a ceramic oscillator, and 0 milliseconds on an external clock. * During normal operation, time-base timer mode, main sleep mode and PLL sleep mode
tRSTL
RST
0.2 VCC 0.2 VCC
* During stop mode
tRSTL
RST
0.2 VCC
90% of amplitude
0.2 VCC
X0
Internal operation clock
Oscillation time of oscillator
500 ns
Oscillation stabilization wait time
Execute instruction Internal reset
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(3) Power-on reset (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Power supply rising time Power supply shutdown time Symbol tR tOFF Pin name Conditions VCC VCC Value Min 0.05 1 Max 30 Unit ms ms Waiting time until power-on Remarks
Notes : * VCC must be lower than 0.2 V before the power supply is turned on. * The above standard is a value for performing a power-on reset. * In the device, there are internal registers which is initialized only by a power-on reset. When the initialization of these items is expected, turn on the power supply according to the standards.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Note : Sudden change of power supply voltage may activate the power-on reset function. When changing the power supply voltage during operation as illustrated below, voltage fluctuation should be minimized so that the voltage rises as smoothly as possible. When raising the power, do not use PLL clock. However, if voltage drop is 1 V/s or less, use of PLL clock is allowed during operation.
VCC
The rising edge should be 50 mV/ms or less. RAM data hold
3.0 V VSS
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MB90335 Series
(4) UART0, UART1 I/O extended serial timing (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock H pulse width Serial clock L pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCKx SCKx SOTx SCKx SINx SCKx SINx SCKx, SINx SCKx, SINx SCKx SOTx SCKx SINx SCKx SINx External shift clock Mode output pin is CL = 80 pF + 1 TTL Internal shift clock Mode output pin is CL = 80 pF + 1 TTL Conditions Value Min 8 tCP - 80 100 60 4 tCP 4 tCP 60 60 Max + 80 150 Unit ns ns ns ns ns ns ns ns ns
Notes : * Above rating is the case of CLK synchronous mode. * CL is a load capacitance value on pins for testing. * tCP is the machine cycle period (unit : ns) . Refer to " (1) Clock input timing". * Internal shift clock mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External shift clock mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
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(5) I2C timing (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter SCL clock frequency (Repeat) [start] condition hold time SDA SCL SCL clock "L" width SCL clock "H" width Repeat [start] condition setup time SCL SDA Data hold time SCL SDA Symbol fSCL tHDSTA tLOW tHIGH tSUSTA tHDDAT Power-supply of external pull-up resistor at 5.0 V fCP*1 20 MHz, R = 1.2 k, C = 50 pF*2 Power-supply of external pull-up resistor at 3.6 V fCP*1 20 MHz, R = 1.0 k, C = 50 pF*2 Power-supply of external pull-up resistor at 5.0 V fCP*1 > 20 MHz, R = 1.2 k, C = 50 pF*2 Power-supply of external pull-up resistor at 3.6 V fCP*1 > 20 MHz, R = 1.0 k, C = 50 pF*2 Power-supply of external pull-up resistor at 5.0 V R = 1.2 k, C = 50 pF*2 Power-supply of external pull-up resistor at 3.6 V R = 1.0 k, C = 50 pF*2 Power-supply of external pull-up resistor at 5.0 V R = 1.2 k, C = 50 pF*2 Power-supply of external pull-up resistor at 3.6 V R = 1.0 k, C = 50 pF*2 Conditions Value Min 0 4.0 4.7 4.0 4.7 0 Max 100 3.45*3 Unit kHz s s s s s
250*4
Data setup time SDA SCL
tSUDAT
ns
200*4
[Stop] condition setup time SCL SDA Bus free time between [stop] condition and [start] condition
tSUSTO
4.0
s
tBUS
4.7
s
*1 : fCP is internal operating clock frequency. Refer to " (1) Clock input timing". *2 : R and C are pull-up resistance of SCL and SDA lines and load capacitance. *3 : The maximum tHDDAT only has to be met if the device does not stretch the "L" width (tLOW) of the SCL signal. *4 : Refer to "* Note of SDA, SCL set-up time".
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MB90335 Series
(6) Timer Input Timing (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol tTIWH tTIWL Pin name PWC Conditions Value Min 4 tCP Max Unit ns
Note : tCP is the machine cycle period (unit : ns) . Refer to " (1) Clock input timing".
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
PWC
tTIWH tTIWL
(7) Timer output timing (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter CLK TOUT change time PPG0 to PPG3 change time Symbol tTO Pin name PPGx Conditions Value Min 30 Max Unit ns
CLK
2.4 V
tTO
PPGx
2.4 V 0.8 V
(8) Trigger Input Timing (VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = -40 C to +85 C) Parameter Input pulse width Symbol tTRGH tTRGL Pin name Conditions INTx Value Min 5 tCP 1 Max Unit ns s Remarks At normal operating At Stop mode
Note : tCP is the machine cycle period (unit : ns) . Refer to " (1) Clock input timing".
0.8 VCC 0.8 VCC 0.2 VCC 0.2 VCC
INTx
tTRGH tTRGL
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MB90335 Series
5. USB characteristics
(VCC = 3.3 V 0.3 V, VSS = 0.0 V, TA = 0 C to +70 C) Parameter Symbol Input High level voltage Input characteristics Input Low level voltage Differential input sensitivity Differential common mode range Output High level voltage Output Low level voltage Cross over voltage Rise time Output characteristics Fall time Rising/falling time matching Output impedance Series resistance Symbol VIH VIL VDI VCM VOH VOL VCRS tFR tLR tFF tLF tRFM tRLM ZDRV RS Value Min 2.0 0.2 0.8 2.8 0.0 1.3 4 75 4 75 90 80 28 25 Max 0.8 2.5 3.6 0.3 2.0 20 300 20 300 111.11 125 44 30 Unit V V V V V V V ns ns ns ns % % Full Speed Low Speed Full Speed Low Speed (TFR/TFF) (TLR/TLF) Including Rs = 27 Recommended value = 27 at using USB* IOH = -200 A IOL = 2 mA Remarks
* : Arrange the series resistance RS values in order to set the impedance value within the output impedance ZSRV. * Data signal timing (Full Speed) Rise time
DVP/HVP DVM/HVM
VCRS 10% 90%
Fall time
90% 10%
tFR
tFF
* Data signal timing (Low Speed) Rise time
HVP HVM
VCRS 10% 90%
Fall time
90% 10%
tLR
tLF
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* Load condition (Full Speed)
RS = 27
ZUSB DVP/HVP
Testing point
CL = 50 pF ZUSB DVM/HVM RS = 27
Testing point
CL = 50 pF
* Load condition (Low Speed)
ZUSB HVP RS = 27
Testing point
CL = 50 pF 150 pF ZUSB HVM RS = 27
Testing point
CL = 50 pF 150 pF
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6. Flash memory write/erase characteristics
Parameter Sector erase time (4 Kbytes sector) Sector erase time (16 Kbytes sector) Chip erase time Word (8 bits width) programming time Program/erase cycle Flash data retention time Average TA = + 85 C TA = + 25 C VCC = 3.0 V Condition Value Min 10000 20 Typ 0.2 0.5 2.6 16 Max 0.5 7.5 3600 Unit s s s s cycle year * Remarks Excludes 00H programming prior to erasure. Excludes 00H programming prior to erasure. Excludes 00H programming prior to erasure. Except for over head time of system
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature measurements into normalized value at + 85 C)
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ORDERING INFORMATION
Part number MB90F337PMC MB90337PMC MB90V330ACR Package 64-pin plastic LQFP (FPT-64P-M23) 299-pin ceramic PGA (PGA-299C-A01) For evaluation Remarks
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MB90335 Series
PACKAGE DIMENSION
64-pin plastic LQFP Lead pitch Package width x package length Lead shape Sealing method Mounting height Code (Reference) 0.65 mm 12.0 x 12.0 mm Gullwing Plastic mold 1.70 mm MAX P-LFQFP64-12x12-0.65
(FPT-64P-M23)
64-pin plastic LQFP (FPT-64P-M23)
14.000.20(.551.008)SQ *12.000.10(.472.004)SQ
48 33
Note 1) * : These dimensions do not include resin protrusion. Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
0.1450.055 (.0057.0022)
49
32
0.10(.004) Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
0.25(.010) INDEX 0~8
64 17
1
16
"A"
0.65(.026)
0.320.05 (.013.002)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.100.10 (.004.004) (Stand off)
0.13(.005)
M
(c)2003-2008 FUJITSU MICROELECTRONICS LIMITED F64034S-c-1-2 C 2003 FUJITSU LIMITED F64034S-c-1-1
Dimensions in mm (inches). Note: The values in parentheses are reference values
Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/package/en-search/
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MEMO
DS07-13735-4E
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MB90335 Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3329 http://jp.fujitsu.com/fml/en/ For further information please contact: North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 E. Arques Avenue, M/S 333 Sunnyvale, CA 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 47, 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 206 Kosmo Tower Building, 1002 Daechi-Dong, Gangnam-Gu, Seoul 135-280, Republic of Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. 151 Lorong Chuan, #05-08 New Tech Park 556741 Singapore Tel : +65-6281-0770 Fax : +65-6281-0220 http://www.fmal.fujitsu.com/ FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm. 3102, Bund Center, No.222 Yan An Road (E), Shanghai 200002, China Tel : +86-21-6146-3688 Fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, 11 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel : +852-2377-0226 Fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office. All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. The company names and brand names herein are the trademarks or registered trademarks of their respective owners. Edited: Sales Promotion Department

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